DAEJEON, South Korea: Panmnesia, a fabless semiconductor company, and Meta, a global hyperscaler, have jointly proposed a next-generation artificial intelligence datacenter architecture in which an entire datacenter operates like a single chip. The work appears as an invited Review in Nature Reviews Electrical Engineering (NREE), a Nature Portfolio journal.

The unit of AI execution is moving from one chip to the whole datacenter

As AI models grow into the trillions of parameters, a single training step can involve hundreds to thousands of accelerators exchanging terabytes of data. Because overall progress is set by the slowest participant, adding accelerators boosts compute capacity, but it also makes the system prone to frequent delays and failures caused by bottlenecking stragglers. When one component responds late, the rest stop and wait - and the wider the range of latency becomes, the harder it is to predict when a job will finish.

Narrowing that spread-and thereby creating a larger, more stable unit of execution-is an industry-wide challenge. Within a rack, devices are already tightly coupled through dedicated high-speed links. The next challenge lies in the segment beyond it - the connection between racks. Today, that segment still relies largely on general-purpose networks such as Ethernet or InfiniBand, where each request must pass through a network interface and a software-based coordination layer, each of which widens latency spread along the way. This work aims to bring greater predictability to this cross-rack segment.

Their foundation is Compute Express Link (CXL), an open industry standard. CXL is developed collaboratively by semiconductor and infrastructure companies, so it can be adopted across the industry without being locked into a single vendor's ecosystem. The architecture proposed by Panmnesia and Meta uses CXL to minimize latency variability beyond the rack. The goal is a datacenter that behaves with the predictability of a single chip.

At the core of the CXL-based architecture: three hardware elements and a hierarchical deployment

The proposed architecture places CPUs, accelerators and memory in a single CXL-based domain, extending the range over which cache coherence is maintained from within the rack to the datacenter as a whole. Three hardware elements - a high-fan-out non-blocking switch, a link acceleration unit (LAU) and a fabric controller - bound latency variability, and the resources themselves are laid out using the same principles that govern the placement of blocks inside a chip. To overcome the physical reach limits of electrical signaling, the Review also sets out how optical links (CXL-over-optics) can extend the reach of a CXL fabric. (Details are given in the Appendix.)

To gauge the effect of the architecture, the Review uses a conventional rack-scale configuration - one CPU coupled to two accelerators - as its reference point. Against that baseline, the number of accelerators a single CPU coordinates rises eightfold, from two to sixteen, and the coherence domain that operates as one unit grows to as many as 960 accelerators, roughly 13 times the reference platform. Accesses that once left the rack to traverse a network now follow a fixed path, with round-trip latency falling from the microsecond range to several hundred nanoseconds - as much as an order of magnitude lower. The unit of replacement after a failure also narrows from a whole server to a single device. Coupling devices at this scale into what behaves as one execution environment would make it possible to train a far larger single AI model without interruption, or to run multiple services concurrently on shared infrastructure without one stalling another.

Review articles in NREE are published by invitation only: the journal identifies a small number of researchers or organizations leading a given field and commissions the work from them. Nature’s selection of Panmnesia as an author on CXL-based datacenter architecture reflects recognition of the company’s technology as representative of the field. Panmnesia is the first semiconductor startup worldwide to lead an NREE Review, and the article is also the journal’s first Review to address CXL technology and AI datacenter architecture.

Myoungsoo Jung, CEO of Panmnesia, said, “As AI systems continue to scale, the ability to connect large numbers of accelerators and memory devices quickly and efficiently is becoming just as important as the performance of individual accelerators. This research outlines a direction for next-generation AI infrastructure, where CXL enables the entire datacenter to operate as a single computing system.”

Panmnesia has already implemented the architecture's core components in silicon, has completed validation, and is now preparing them for commercial supply. The Review is available at the link below.
https://www.nature.com/articles/s44287-026-00315-5

Fonte: Business Wire